1. Field of the Invention
The present invention relates to a pseudo locked state detection system for detecting and preventing a pseudo locked state from occurring in a quadrature demodulation circuit used for digital television broadcasting.
2. Description of Related Art
The technology for supplying digital television broadcasting signals having been practically implemented, commercial digital television broadcasting has begun. Commercial digital television broadcasting can be broadly divided into either broadcasting where digital television signals are transmitted by satellite or broadcasting using terrestrial waves. In the following, satellite digital television broadcasting will be described.
FIG. 5 illustrates a structure of one frame of digital data to be received in a satellite digital broadcasting receiver. One frame of digital data as depicted in FIG. 5 contains 39936 symbols, a symbol as used herein referring to a signal received in synchronization with one clock. The leading end portion of one frame includes a transmission multiple control (TMCC) signal for transmitting control information regarding a slot signal or a transmission system, and a synchronization word signal. The synchronization word signal contains a total of 40 symbols, while the number of symbols in the TMCC and synchronizing word signals totals 192, which are to be transmitted as a BPSK (binary PSK) modulation signal.
After the TMCC signal and the synchronization word signal, data (containing separate tracks such as video, audio, or the like) and carrier clock burst signals are alternately provided. Each data portion contains 203 symbols and each carrier clock burst signal contains 4 symbols. A carrier clock burst signal is a BPSK modulation signal.
A data portion containing 203 symbols and a carrier clock burst signal portion containing 4 symbols constitute one set of data, and 4 sets in succession, ((203+4)xc3x974) symbols, is referred to as one xe2x80x9cslotxe2x80x9d.
Slots are modulated using different types of modulation. The type of modulation used and the order of data transmission are recognized after drawing frequency of the carrier clock has been determined, by detecting a synchronization word, establishing a frame synchronization, and demodulating the TMCC. The modulation types to be used include 8PSK, QPSK (Quadrature PSK), BPSK, or the like.
FIG. 6 illustrates a structure of a satellite digital broadcasting receiver. A digital television signal transmitted from a satellite is received by a tuner 61 where synchronous detection is applied while the frequency is down-converted. A digital modulation signal obtained from the tuner 61 is demodulated in a quadrature demodulation circuit 62 to produce I and Q baseband signals. A PSK demodulation circuit 63 provides various types of PSK demodulation according to the I and Q baseband signals, and an error correction circuit 64 applies error correction to a PSK demodulation signal. The PSK demodulation signal subjected to error correction is decoded into motion image data or audio data in a signal processing circuit 65 according to set protocols such as those of the MPEG1 or MPEG2 system.
In a digital broadcasting receiver having a configuration as shown in FIG. 3, I and Q baseband signals are demodulated from a digital television signal. As shown in FIG. 3, adders 1 and 2 apply quasi synchronous detection to a digital television signal and respectively output an I signal and a Q signal. The I signal, only a low frequency component of which passes through an LPF 3, is converted into a digital value in an AD converter 4 and is input to a demodulator 6 via a matched filter 5. Similarly, the Q signal, again only a low frequency component of which passes through an LPF 7, is converted into a digital value in an AD converter 8 and is input to the demodulator 6 via a matched filter 9.
The demodulator 6 outputs I and Q baseband signals demodulated with a reproduced carrier. Carrier reproduction is performed by detecting a frequency shift of the I and Q baseband signals. Namely, the I and Q baseband signals are input to a phase error detection circuit 10 to be compared with I and Q baseband signals from one clock before to obtain a phase angle difference. A phase error of the received signal is detected by using this difference, and is applied to an NCO circuit 11 which then outputs a frequency signal fp in accordance with the phase error, and the frequency signal fp is further fed back to the demodulator 6. In accordance with the frequency signal fp, complex multiplication is applied to the input I and Q signals. The demodulator 6 corrects the vectors of the I and Q signals and outputs the corrected signals as the I and Q baseband signals, to which signal processing such as error correction is carried out by an error detection/correction circuit 12 provided downstream of the demodulator 6.
With the configuration FIG. 3, when a frequency difference between a local oscillation signal fr and a modulation carrier signal fc to be applied to the multipliers 1 and 2 is xcex94f, the following equation (1) is obtained.
xcex94f=|frxe2x88x92fc|xe2x80x83xe2x80x83(1)
When xcex94f=0, correct baseband signals can consistently be obtained without any correction in the demodulator 6. Specifically, in the case of QPSK modulation, the baseband signals can consistently be obtained at points indicated by xe2x97xaf in a signal space view shown in FIG. 4. When xcex94fxe2x89xa00, on the other hand, the phase of a baseband signal shifts while the phase amount is continuously changing. Namely, the phase of the vector of a baseband signal rotates around the circle in FIG. 4. Therefore, the carrier reproduction loop controls the output frequency fp of the NCO circuit such that |xcex94fxe2x88x92fp|=0, to thereby realize the baseband signals at the points xe2x97xaf as shown in FIG. 4 by preventing the phase of the baseband signals of the demodulator 6 from rotating.
However, pseudo-lock occurs in the carrier reproduction loop of the demodulator 6 when the following frequency relationship is established, where a reproduction clock is represented by fsym.
|xcex94fxe2x88x92fp|=mxc3x97fsym/2nxe2x80x83xe2x80x83(2)
where m and n are integer values, and an integer n changes depending on the demodulation type. For instance, n=1 in the BPSK modulation, n=2, in the QPSK modulation, and n=3 in the 8PSK modulation. When the phase of a baseband signal at point A shifts 360xc2x0 and returns back to the point A during the reproduction clock period as shown in FIG. 4, for example, no phase shift is apparent. Because the actual phase shift is not detected, a pseudo carrier locked state in which the carrier reproduction loop acts as if locked occurs. In this state, although a baseband signal can be demodulated, the baseband signal does not contain correct data.
Since the phase of the baseband signal vector is detected after shifting the vector to the first quadrant in FIG. 4, the phase shift amount of a baseband signal which will cause a pseudo carrier locked state differs depending on the modulation type. In the case of the QPSK modulation in which the baseband signals exist at the four points in FIG. 4 indicated by xe2x97xaf, pseudo carrier lock occurs even with a phase shift of mxc3x97fsym/4.
A conventional method of detecting a pseudo carrier lock will also be described with reference to FIG. 3. Referring to FIG. 3, there are provided the error detection/correction circuit 12 for detecting and correcting an error of a baseband signal from the demodulator 6, and a CPU 13 for detecting a pseudo carrier lock state according to detection signals from the phase error detection circuit 10 and the error detection/correction circuit 12. When a pseudo carrier locked state occurs, the baseband signal does not contain correct data and the error detection/correction circuit 12 produces an error detection signal. The CPU 13, receiving this error detection signal and a lock detection signal generated by the phase error detection circuit 10 when the carrier reproduction loop is locked, determines the pseudo carrier locked state.
Upon detecting the pseudo carrier locked state, the CPU 13 changes the number of dividing of a programmable divider 15 in a PLL circuit for channel (broadcast station) selection until the pseudo carrier locked state is released. The local oscillation frequency fc is changed by thus changing the divisor to thereby break the frequency relationship defined in the above equation (1). The carrier reproduction loop temporarily enters an unlocked state for drawing a correct carrier lock because the PLL circuit will be locked at a different frequency.
In the example described above, however, since the pseudo carrier locked state is detected by software operating in the CPU 13, the CPU 13 must continuously monitor both the lock detection signal and the error detection signal. Namely, a conventional structure requires continuous monitoring of the pseudo carrier locked state by the software of the CPU 13, imposing a significant burden on the software. Further, because the interface of the CPU 13 is for serial data, a significant amount time is required for data reception, and it is difficult to quickly detect the pseudo locked state because such detection is executed by the software.
The present invention aims to provide a circuit which simply and rapidly detect a pseudo locked state of a reproduction clock.
According to the present invention, in a locked state of a reproduction clock, the state of establishment of frame synchronization is determined. In a pseudo locked state, data is not correctly demodulated and therefore frame synchronization cannot be established. Thus, a pseudo locked state can be easily determined by the detection of frame synchronization.
Frame synchronization is always detected whenever data is received. Therefore, this circuit is also utilized for detecting whether or not frame synchronization is established to thereby eliminate the need for any extra circuits.
Data in accordance with a phase difference causing a pseudo locked state, which is known in advance, is stored in a correction memory and is read out as correction data when a pseudo locked state is detected, thereby enabling correction processing to be rapidly performed. In particular, such a structure can be easily implemented by hardware.